Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - VHDL countdown

Search list

[Other] trafficlight

Description: VHDL编写的交通灯程序，有倒计时功能，数字电路课程设计，内附状态图和dofile波形模拟！-VHDL prepared by the traffic lights procedures, the countdown function, digital circuit design courses, enclosing a state map and dofile waveform simulation!
Platform: | Size: 4096 | Author: 张傻 | Hits:

[VHDL-FPGA-Verilog] traffic

Description: xilinx完成一个模拟的十字路口交通信号灯，主干道上的绿灯时间为30s，支干道的绿灯时间为30s，且交通灯从绿变红时，有6s黄灯亮的时间间隔。当然每种状态的倒计时的时间值应显示到LED数码管上。-Xilinx completed in a simulated traffic lights at a crossroads, a main road on the green time for the 30s, branch roads green time for 30s, and red traffic lights from green when 6s yellow light time interval. Of course, each state s countdown time value should be shown on the LED digital tube.
Platform: | Size: 95232 | Author: haolj | Hits:

[Education soft system] time_out

Description: 我的课程设计，可预置倒计时显示系统。该系统可以预置100以内任意时间，倒计时，有数码管显示，开始时是5s显示一次，最好5s是每s显示一次-My curriculum design, can be preset countdown display system. The system can be preset to 100 within an arbitrary time, the countdown, there are digital display, at the beginning, is 5s show, the best way 5s per s showed a
Platform: | Size: 194560 | Author: 吴小明 | Hits:

[VHDL-FPGA-Verilog] qiangdaqi

Description: 实现抢答器功能，30秒的倒数，抢答控制均可以，-Answer to achieve function, 30 seconds of the countdown for the Answer can be controlled,
Platform: | Size: 243712 | Author: 涂亮 | Hits:

[Documents] atrafficlightrealizedbyFPGA

Description: 一篇用VHDL实现的交通灯设计，具有灯种显示和倒计时功能-Realize with a VHDL design of traffic lights with light display and a countdown function
Platform: | Size: 860160 | Author: Roger | Hits:

[SCM] lift

Description: 功能完善的四层电梯程序。开门停8秒，上升或者下降一层用时5秒，有五秒倒计时数码管，楼层显示数码管，以及电梯内外楼层请求显示灯。-A well-functioning procedures for four-storey elevator. 8 seconds to open the door stopped, increased or decreased when a layer of 5 seconds, the 5 seconds countdown digital tube, digital tube display floor, as well as inside and outside the elevator floor indicator lights request.
Platform: | Size: 1024 | Author: 韩代榕 | Hits:

[Other] Trafficlight

Description: 系统设置一个两位BCD码倒计时计数器（计数脉冲1HZ），用于记录各状态持续时间； 因为各状态持续时间不一致，所以上述计数器应置入不同的预置数； 倒计时计数值输出至二个数码管显示； 程序共设置4个进程： ① 进程P1、P2和P3构成两个带有预置数功能的十进制计数器，其中P1和P3分别为个位和十位计数器，P2产生个位向十位的进位信号； ② P4是状态寄存器，控制状态的转换，并输出6盏交通灯的控制信号。-System to set up a two BCD code countdown counter (count pulse 1HZ), used to record the duration of each state because the duration of each state are inconsistent, so these counters should be placed in several different presets countdown of numerical output to two digital display procedures were set up four processes: ① process P1, P2 and P3 form two functions with a preset number of decimal counters, of which P1 and P3, respectively, for months, and 10-bit counters, P2 to generate a 10-bit The binary signal ② P4 is the status register, control the state of the conversion, and six output control signals of traffic lights.
Platform: | Size: 1024 | Author: kid | Hits:

[ARM-PowerPC-ColdFire-MIPS] demo

Description: Flex chip implementation File: UP2FLEX JTAG jumper settings: down, down, up, up Input: Reset - FLEX_PB1 Input n - FLEX_SW switches 1 to 8 Output: Countdown - two 7-segment LEDs. Done light - decimal point on Digit1. Operation: Setup the binary input n number. Press the Reset switch. See the countdown from n down to 0 on the 7-segment LEDs. Done light lit when program terminates.-Flex chip implementation File: UP2FLEX JTAG jumper settings: down, down, up, up Input: Reset- FLEX_PB1 Input n- FLEX_SW switches 1 to 8 Output: Countdown- two 7-segment LEDs. Done light- decimal point on Digit1. Operation: Setup the binary input n number. Press the Reset switch. See the countdown from n down to 0 on the 7-segment LEDs. Done light lit when program terminates.
Platform: | Size: 107520 | Author: james | Hits:

[assembly language] jioatongdeng

Description: 实现交通灯的基本功能，包括，红绿灯，特殊事件处理，倒计时等-The realization of the basic functions of traffic lights, including traffic lights, special event handling, countdown, etc.
Platform: | Size: 101376 | Author: xianxu | Hits:

[Software Engineering] qiangda

Description: l、设计用于竞赛的四人抢答器，功能如下： (1) 有多路抢答器，台数为四； (2) 具有抢答开始后20秒倒计时，20秒倒计时后无人抢答显示超时，并报警； (3) 能显示超前抢答台号并显示犯规警报； (4) 能显示各路得分，并具有加、减分功能； 2、系统复位后进入抢答状态，当有一路抢答键按下时，该路抢答信号将其余各路抢答封锁，同时铃声响，直至该路按键松开，显示牌显示该路抢答台号。 3、用VHDL语言设计符合上述功能要求的四人抢答器，并用层次设计方法设计该电路 -l, designed for Answer four contests, and features are as follows: (1) Answer the way how, and the number to four (2) Answer 20 seconds after the beginning of the countdown, countdown to 20 seconds after the Answer shows no overtime, and report to the police (3) can show in advance Answer Desk No. foul alarm and display (4) can display various scoring with Canada, by sub-function 2, the system reset after entering the Answer state, all the way when pressing the Answer key , the signals will be the rest of the way each Answer Answer blockade, ring tones at the same time, release the button until the road, the road signs showing the number Answer Desk. 3, using VHDL language design meets the functional requirements of the above Answer four devices, and design method-level design of the circuit
Platform: | Size: 305152 | Author: hugh | Hits:

[SCM] qiangdaqi

Description: 四人抢答器设计,具有超前抢答显示报警，20秒倒计时超时抢答报警及加分、减分等功能-Answer four design, with advance Answer show alarm, countdown to 20 seconds of overtime Answer alarm and extra points, reducing the classification function
Platform: | Size: 2048 | Author: 小草 | Hits:

[VHDL-FPGA-Verilog] travel

Description: 自己做的vhdl课程设计，交通灯：实现主干道倒计时，分别为30,20,5秒，分情况：当主干道有车时，红黄绿交替，当只一个道路上有车时，那个道的交通灯变绿色，利用max+plus2做成，使用flex8000,epf8282alc84_4只用加一个38译码器模块即可，使用别的板子也可以运行-VHDL to do their own curriculum design, traffic lights: the realization of the trunk road countdown, 30,20,5 seconds, respectively, sub-cases: When there are car trunk, red, yellow, and green alternately, when there is only a road car, the Road change traffic lights green, the use of max+ plus2 make, use flex8000, epf8282alc84_4 only 38 plus a decoder module can, use the other board can also run
Platform: | Size: 529408 | Author: 安治州 | Hits:

[Other] countdown

Description: 基于VHDL语言的倒计时模块程序，1Hz时钟-Based on the VHDL language countdown module procedures, 1Hz clock
Platform: | Size: 4096 | Author: lynn hu | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 实现一个10秒倒计时电路，要求使用8*8点阵显示计时结果。在QuartusII平台上设计程序和仿真题目要求，并下载到实验板验证实验结果。-Achieve a 10-second countdown circuit, requires the use of 8* 8 dot matrix display timing results. QuartusII platform in the design process and simulation on the subject request and download to the board to verify the experimental results.
Platform: | Size: 404480 | Author: li | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: 24秒倒计时设计用于专业篮球比赛有说明和一系列程序代码-24 seconds countdown designed for professional basketball game and a series of procedures has made it clear that the code
Platform: | Size: 9216 | Author: 米虫 | Hits:

[Other] project3

Description: 用VHDL语言实现一个10秒倒计时电路，要求使用8*8点阵显示计时结果-VHDL language used to achieve a 10 seconds countdown circuits require the use of 8* 8 dot matrix display timing results
Platform: | Size: 296960 | Author: eefamily | Hits:

[Other] trafficlight

Description: 十字路口交通灯设计，实现红绿灯交替转换，并且具有倒计时功能，用于显示时间-Design of traffic lights at the crossroads, the traffic lights turn to achieve the conversion, and has a countdown function, used to display time
Platform: | Size: 541696 | Author: ghost | Hits:

[VHDL-FPGA-Verilog] FPGArealiztionofdigitalsignalprocessing

Description: 数字信号处理FPGA实现 实用程序和文件,有sine.exe ---输入宽度。输出对应的正弦波表 mif文件 csd.exe --- 寻找整数和分数的标准有符号数字量（canonical signed digit ，CSD）表达式程序 fpinv.exe --- 倒数计算浮点数表的程序 dagen.exe ---分布式算法文件生成HDL" onclick="tagshow(event)" class="t_tag">VHDL代码的程序 cic.exe ---CIC滤波器计算参数的程序 -Digital Signal Processing FPGA realization of practical procedures and documents, there are sine.exe--- input width. Sine wave output of the corresponding csd.exe--- Table mif file to find the integer and fractional number of the volume of standard symbols (canonical signed digit, CSD) Expression Programming fpinv.exe--- countdown procedures for calculation of floating-point form dagen.exe--- documents distributed algorithm to generate HDL " onclick =" tagshow (event) " class =" t_tag " > VHDL program code cic.exe--- CIC filter process parameters
Platform: | Size: 260096 | Author: kevin | Hits:

[SCM] qiangdaqi

Description: 　 (1) 抢答器线路测试功能 　　为了保证比赛的正常进行，比赛前需要调试线路能否正常工作。 　　 (2) 第一抢答信号的鉴别和锁存功能 　　可以判断谁最先抢到回答的资格，其相应的绿灯表示抢答成功，并具有锁存功能，一直到下一题开始。 　　 (3) 犯规警示功能 　　可以判断出参赛者有没有在主持人读题的期间按下抢答器，有则相应的红灯亮，同时取消其本轮抢答资格。 　　 (4) 计时功能 　　可以预置时间，可以进行倒计时并且将时间显示出来。 　　 (5) 计分功能 可以实现加分，并且显示出来 -(1) Answer line testing device in order to ensure the normal game, the need to debug line before the game can work properly. (2) Answer the first to identify and latch signals to determine who can be the first to get the qualifications to answer, and its corresponding Answer green that success and with latch function, until the beginning of the next title. (3) foul warning function can be judged contestants have read in the host during the press Answer questions, and there is a corresponding red light, at the same time cancel the current round of qualifications Answer. (4) The time functions can be preset time, the countdown can be displayed and the time. (5) scoring function points can be achieved and displayed.
Platform: | Size: 956416 | Author: 孙国栋 | Hits:

[VHDL-FPGA-Verilog] qdq

Description: （1）用于竞赛强大的四人抢答器 （2）抢答开始后20秒倒计，倒计结束后无人抢答显示超时 （3）能显示抢答台号 （4）系统复位后进入抢答状态，能显示犯规警报-(1) is used to contest a powerful four Responder (2) to answer in 20 seconds after the start of countdown, countdown display time-out after no one to answer in (3) can show to answer in station ID (4), enter the answer in the state after a system reset capable of displaying foul alert
Platform: | Size: 702464 | Author: | Hits:
« 12 3 4 »

CodeBus www.codebus.net